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1 1998 integrated device technology, inc. dsc-2679/7 ? december 1998 cmos asychronous fifo 256 x 9, 512 x 9, 1,024 x 9 IDT7200L idt7201la idt7202la features: ? first-in/first-out dual-port memory ? 256 x 9 organization (idt7200) ? 512 x 9 organization (idt7201) ? 1,024 x 9 organization (idt7202) ? low power consumption active: 440mw (max.) power-down: 28mw (max.) ? ultra high speed12ns access time ? asynchronous and simultaneous read and write ? fully expandable by both word depth and/or bit width ? pin and functionally compatible with 720x family ? status flags: empty, half-full, full ? auto-retransmit capability ? high-performance cemos? technology ? military product compliant to mil-std-883, class b ? standard military drawing #5962-87531, 5962-89666, 5962-89863 and 5962-89536 are listed on this function ? dual versions available in the tssop package. for more informa- tion, see idt7280/7281/7282 data sheet (3208.pdf) idt7280 = 2 x idt7200 idt7281 = 2 x idt7201 idt7282 = 2 x idt7202 ? industrial temperature range (C40 o c to +85 o c) is available (plastic packages only) description: the idt7200/7201/7202 are dual-port memories that load and empty data on a first-in/first-out basis. the devices use full and empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. the reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. data is toggled in and out of the devices through the use of the write ( w ) and read ( r ) pins. the devices utilize a 9-bit wide data array to allow for control and parity bits at the users option. this feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. it also features a retransmit ( rt ) capability that allows for reset of the read pointer to its initial position when rt is pulsed low to allow for retransmission from the beginning of data. a half-full flag is available in the single device mode and width expansion modes. these fifos are fabricated using idts high-speed cmos technology. they are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. military grade product is manufactured in compliance with the latest revision of mil-std-883, class b. functional block diagram w write control read control r flag logic expansion logic xi write pointer ram array 256 x 9 512 x 9 1,024 x 9 read pointer data inputs reset logic three- state buffers data outputs ef ff xo / hf rs fl / rt (d 0 -d 8 ) 2679 drw 01 (q 0 -q 8 )
2 idt IDT7200L/7201la/7202la pin configurations recommended dc operating conditions symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v commercial/industrial/military gnd supply voltage 0 0 0 v v ih (1) input high voltage 2.0 v commercial/industrial v ih (1) input high voltage 2.2 v military v il (2) input low voltage 0.8 v commercial/industrial/military t a operating temperature 0 70 o c commercial t a operating temperature C40 85 o c industrial t a operating temperature C55 125 o c military notes: 2679 tbl 03 1. for rt / rs / xi input, v ih = 2.6v (commercial). for rt / rs / xi input, v ih = 2.8v (military). 2. 1.5v undershoots are allowed for 10ns once per cycle. absolute maximum ratings symbol rating coml & ind'l mil. unit v term terminal voltage C0.5 to +7.0 C0.5 to +7.0 v with respect to gnd t stg storage C55 to +125 C65 to +155 o c temperature i out dc output C50 to +50 C50 to +50 ma current note: 2679 tbl 01 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. reference order package type identifier code plastic dip (1) p28-1 p plastic thin dip p28-2 t p cerdip (1) d28-1 d thin cerdip d28-3 t d soic so28-3 so cerpack (1) e28-2 xe top view reference order package type identifier code lcc (1) l32- 1 l plcc j32-1 j top view note: 1. the 600-mil-wide dip (p28-1 and d28-1), cerpack and lcc are not available for the idt7200. w d 8 v cc d 4 1 2 28 27 d 3 d 5 326 d 2 d 6 425 d 1 d 7 524 d 0 fl / rt 623 xi rs 722 ff ef 821 q 0 xo / hf 920 q 1 q 7 10 19 q 2 q 6 11 18 q 3 q 5 12 17 q 8 q 4 13 16 gnd r 14 15 2679 drw 02a d 2 5 d 1 6 d 0 7 xi 8 ff 9 q 0 10 q 1 11 nc 12 q 2 13 d 6 d 7 nc fl / rt rs ef xo / hf q 7 q 6 29 28 27 26 25 24 23 22 21 4 3 2 1 32 31 30 14 15 16 17 18 19 20 q 3 q 8 gnd nc r q 4 q 5 d 3 d 8 w nc v cc d 4 d 5 index 2679 drw 02b
3 idt IDT7200L/7201la/7202la dc electrical characteristics (commercial: v cc = 5v 10%, t a = 0 o c to +70 o c; industrial: v cc = 5v 10%, t a = C40 o c to +85 o c; military: v cc = 5v 10%, t a = C55 o c to +125 o c) IDT7200L IDT7200L idt7201la idt7201la idt7202la idt7202la com'l & ind'l (1) military t a = 12, 15, 20, 25, 35, 50 ns t a = 20, 30, 40, 50, 65, 80, 120 ns symbol parameter min. max. min. max. unit i li (2) input leakage current (any input) C1 1 C10 10 a i lo (3) output leakage current C10 10 C10 10 a v oh output logic 1 voltage i oh = C2ma 2.4 2.4 v v ol output logic 0 voltage i ol = 8ma 0.4 0.4 v i cc1 (4,5,6) active power supply current 80 100 ma i cc2 (4,7) standby current ( r = w = rs = fl / rt =v ih ) 5 15ma notes: 2679 tbl 05 1. industrial temperature range product for the 25 ns speed grade is available as a standard device. all other speed grades are available by special order. 2. measurements with 0.4 v in v cc . 3. r 3 v ih , 0.4 v out v cc . 4. tested with outputs open (i out = 0). 5. tested at f = 20 mhz. 6. typical i cc1 = 15 + 2*f s + 0.02*c l *f s (in ma) with v cc = 5v, t a = 25 o c, f s = wclk frequency = rclk frequency (in mhz, using ttl levels), data switching at f s /2, c l = capacitive load (in pf). 7. all inputs = v cc - 0.2v or gnd + 0.2v. ac test conditions input pulse levels gnd to 3.0v input rise/fall times 5ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 1 2679 tbl 08 symbol parameter condition max. unit c in input capacitance v in = 0v 8 pf c out output capacitance v out = 0v 8 pf note: 2679 tbl 02 1. characterized values, not currently tested. capacitance (t a = +25 o c, f = 1.0 mhz) or equivalent circuit 2679 drw 03 30pf* 1.1k 5v to output pin 680 w figure 1. output load * includes scope and jig capacitances.
4 idt IDT7200L/7201la/7202la ac electrical characteristics (1) (commercial: v cc = 5v 10%, t a = 0 o c to +70 o c; industrial: v cc = 5v 10%, t a = C40 o c to +85 o c; military: v cc = 5v 10%, t a = C55 o c to +125 o c) commercial com'l & mil. com'l & ind'l (2) military com'l 7200l12 7200l15 7200l20 7200l25 7200l30 7200l35 7201la12 7201la15 7201la20 7201la25 7201la30 7201la35 7202la12 7202la15 7202la20 7202la25 7202la30 7202la35 symbol parameter min. max. min. max. min. max. min. max. min. max. min. max. unit t s shift frequency 50 40 33.3 28.5 25 22.2 m h z t rc read cycle time 20 25 30 35 40 45 ns t a access time 12 15 20 25 30 35 ns t rr read recovery time 8 10 10 10 10 10 ns t rpw read pulse width (3) 12 15 20 25 30 35 ns t rlz read pulse low to data bus at low z (4) 3 3 3 3 33 ns t wlz write pulse high to data bus at low z (4,5) 5 5 5 5 55 ns t dv data valid from read pulse high 5 5 5 5 5 5 ns t rhz read pulse high to data bus at high z (4) 12 15 15 18 20 20 ns t wc write cycle time 20 25 30 35 40 45 ns t wpw write pulse width (3) 12 15 20 25 30 35 ns t wr write recovery time 8 10 10 10 10 10 ns t ds data set-up time 9 11 12 15 18 18 ns t dh data hold time 0 0 0 0 0 0 ns t rsc reset cycle time 20 25 30 35 40 45 ns t rs reset pulse width (3) 12 15 20 25 30 35 ns t rss reset set-up time (4) 12 15 20 25 30 35 ns t rsr reset recovery time 8 10 10 10 10 10 ns t rtc retransmit cycle time 20 25 30 35 40 45 ns t rt retransmit pulse width (3) 12 15 20 25 30 35 ns t rts retransmit set-up time (4) 12 15 20 25 30 35 ns t rtr retransmit recovery time 8 10 10 10 10 10 ns t efl reset to empty flag low 12 25 30 35 40 45 ns t hfh,ffh reset to half-full and full flag high 17 25 30 35 40 45 ns t rtf retransmit low to flags valid 20 25 30 35 40 45 ns t ref read low to empty flag low 12 15 20 25 30 30 ns t rff read high to full flag high 14 15 20 25 30 30 ns t rpe read pulse width after ef high 12 15 20 25 30 35 ns t wef write high to empty flag high 12 15 20 25 30 30 ns t wff write low to full flag low 14 15 20 25 30 30 ns t whf write low to half-full flag low 17 25 30 35 40 45 ns t rhf read high to half-full flag high 17 25 30 35 40 45 ns t wpf write pulse width after ff high 12 15 20 25 30 35 ns t xol read/write to xo low 12 15 20 25 30 35 ns t xoh read/write to xo high 12 15 20 25 30 35 ns t xi xi pulse width (3) 12 15 20 25 30 35 ns t xir xi recovery time 8 10 10 10 10 10 ns t xis xi set-up time 8 10 10 10 10 10 ns notes: 2679 tbl 06 1. timings referenced as in ac test conditions. 2. industrial temperature range is available by special order for speed grades faster than 25ns. 3. pulse widths less than minimum value are not allowed. 4. values guaranteed by design, not currently tested. 5. only applies to read data flow-through mode.
5 idt IDT7200L/7201la/7202la ac electrical characteristics (1) (continued) (commercial: v cc = 5v 10%, t a = 0 o c to +70 o c; industrial: v cc = 5v 10%, t a = C40 o c to +85 o c; military: v cc = 5v 10%, t a = C55 o c to +125 o c) military com'l & mil. military (2) 7200 l40 7200l50 7200l65 7200l80 7200l120 7201la40 7201la50 7201la65 7201la80 7201la120 7202la40 7202la50 7202la65 7202la80 7202la120 symbol parameter min. max. min. max. min. max. min. max. min. max. unit t s shift frequency 20 15 12.5 10 7 mhz t rc read cycle time 50 65 80 100 140 ns t a access time 40 50 65 80 120 ns t rr read recovery time 10 15 15 20 20 ns t rpw read pulse width (3) 40 50 65 80 120 ns t rlz read pulse low to data bus at low z (4) 3 3 33 3 ns t wlz write pulse high to data bus at low z (4, 5) 5 5 55 5 ns t dv data valid from read pulse high 5 5 5 5 5 ns t rhz read pulse high to data bus at high z (4) 25 30 30 30 35 ns t wc write cycle time 50 65 80 100 140 ns t wpw write pulse width (3) 40 50 65 80 120 ns t wr write recovery time 10 15 15 20 20 ns t ds data set-up time 20 30 30 40 40 ns t dh data hold time 0 5 10 10 10 ns t rsc reset cycle time 50 65 80 100 140 ns t rs reset pulse width (3) 40 50 65 80 120 ns t rss reset set-up time (4) 40 50 65 80 120 ns t rsr reset recovery time 10 15 15 20 20 ns t rtc retransmit cycle time 50 65 80 100 140 ns t rt retransmit pulse width (3) 40 50 65 80 120 ns t rts retransmit set-up time (4) 40 50 65 80 120 ns t rtr retransmit recovery time 10 15 15 20 20 ns t efl reset to empty flag low 50 65 80 100 140 ns t hfh,ffh reset to half-full and full flag high 50 65 80 100 140 ns t rtf retransmit low to flags valid 50 65 80 100 140 ns t ref read low to empty flag low 30 45 60 60 60 ns t rff read high to full flag high 35 45 60 60 60 ns t rpe read pulse width after ef high 40 50 65 80 120 ns t wef write high to empty flag high 35 45 60 60 60 ns t wff write low to full flag low 35 45 60 60 60 ns t whf write low to half-full flag low 50 65 80 100 140 ns t rhf read high to half-full flag high 50 65 80 100 140 ns t wpf write pulse width after ff high 40 50 65 80 120 ns t xol read/write to xo low 40 50 65 80 120 ns t xoh read/write to xo high 40 50 65 80 120 ns t xi xi pulse width (3) 40 50 65 80 120 ns t xir xi recovery time 10 10 10 10 10 ns t xis xi set-up time 10 15 15 15 15 ns notes: 2679 tbl 07 1. timings referenced as in ac test conditions 2. speed grades 65, 80 and 120 not available in the cerpack 3. pulse widths less than minimum value are not allowed. 4. values guaranteed by design, not currently tested. 5. only applies to read data flow-through mode.
6 idt IDT7200L/7201la/7202la device mode, this pin acts as the retransmit input. the single device mode is initiated by grounding the expansion in ( xi ). the idt7200/7201a/7202a can be made to retransmit data when the retransmit enable control ( rt ) input is pulsed low. a retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. read enable ( r ) and write enable ( w ) must be in the high state during retransmit. this feature is useful when less than 256/512/1,024 writes are performed between resets. the retransmit feature is not compatible with the depth expansion mode and will affect the half-full flag ( hf ), depending on the relative locations of the read and write pointers. expansion in ( xi xi xi xi xi ) this input is a dual-purpose pin. expansion in ( xi ) is grounded to indicate an operation in the single device mode. expansion in ( xi ) is connected to expansion out ( xo ) of the previous device in the depth expansion or daisy chain mode. outputs: full flag ( ff ff ff ff ff ) the full flag ( ff ) will go low, inhibiting further write operation, when the write pointer is one location less than the read pointer, indicating that the device is full. if the read pointer is not moved after reset ( rs ), the full-flag ( ff ) will go low after 256 writes for idt7200, 512 writes for the idt7201a and 1,024 writes for the idt7202a. empty flag ( ef ef ef ef ef ) the empty flag ( ef ) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. expansion out/half-full flag ( xo xo xo xo xo / hf hf hf hf hf ) this is a dual-purpose output. in the single device mode, when expansion in ( xi ) is grounded, this output acts as an indication of a half-full memory. after half of the memory is filled and at the falling edge of the next write operation, the half-full flag ( hf ) will be set low and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. the half-full flag ( hf ) is then reset by using rising edge of the read operation. in the depth expansion mode, expansion in ( xi ) is connected to expansion out ( xo ) of the previous device. this output acts as a signal to the next device in the daisy chain by providing a pulse to the next device when the previous device reaches the last location of memory. data outputs (q 0 C q 8 ) data outputs for 9-bit wide data. this data is in a high impedance condition whenever read ( r ) is in a high state. signal descriptions inputs: data in (d 0 C d 8 ) data inputs for 9-bit wide data. controls: reset ( rs rs rs rs rs ) reset is accomplished whenever the reset ( rs ) input is taken to a low state. during reset, both internal read and write pointers are set to the first location. a reset is required after power up before a write operation can take place. both the read enable ( r r r r r ) and write enable ( w w w w w ) inputs must be in the high state during the window shown in figure 2, (i.e., t rss before the rising edge of rs rs rs rs rs ) and should not change until t rsr after the rising edge of rs rs rs rs rs . half-full flag ( hf hf hf hf hf ) will be reset to high after reset ( rs rs rs rs rs ). write enable ( w w w w w ) a write cycle is initiated on the falling edge of this input if the full flag ( ff ) is not set. data set-up and hold times must be adhered to with respect to the rising edge of the write enable ( w ). data is stored in the ram array sequentially and independently of any on-going read operation. after half of the memory is filled and at the falling edge of the next write operation, the half-full flag ( hf ) will be set to low and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. the half-full flag ( hf ) is then reset by the rising edge of the read operation. to prevent data overflow, the full flag ( ff ) will go low, inhibiting further write operations. upon the completion of a valid read operation, the full flag ( ff ) will go high after t rff , allowing a valid write to begin. when the fifo is full, the internal write pointer is blocked from w , so external changes in w will not affect the fifo when it is full. read enable ( r r r r r ) a read cycle is initiated on the falling edge of the read enable ( r ) provided the empty flag ( ef ) is not set. the data is accessed on a first- in/first-out basis, independent of any ongoing write operations. after read enable ( r ) goes high, the data outputs (q 0 C q 8 ) will return to a high impedance condition until the next read operation. when all data has been read from the fifo, the empty flag ( ef ) will go low, allowing the final read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. once a valid write operation has been accomplished, the empty flag ( ef ) will go high after t wef and a valid read can then begin. when the fifo is empty, the internal read pointer is blocked from r so external changes in r will not affect the fifo when it is empty. first load/retransmit ( fl fl fl fl fl / rt rt rt rt rt ) this is a dual-purpose input. in the depth expansion mode, this pin is grounded to indicate that it is the first loaded (see operating modes). in the single
7 idt IDT7200L/7201la/7202la notes: 1. ef , ff , hf may change status during reset, but flags will be valid at t rsc . 2. w and r = v ih around the rising edge of rs . figure 2. reset figure 4. full flag from last write to first read figure 3. asynchronous write and read operation w rs r ef hf , ff t rsc t rs t rss t rss t rsr t efl t hfh , t ffh 2679 drw 04 t a r t rc data out valid data out valid t rpw t rlz t dv t a t rhz t rr t wc t wr t wpw data in valid data in valid t ds t dh q 0 -q 8 2679 drw 05 w d 0 -d 8 last write r ignored write first read additional reads w ff t wff t rff first write 2679 drw 06
8 idt IDT7200L/7201la/7202la last read r ignored read first write additional writes w ef t wef valid t a data out t ref 2679 drw 07 first read valid figure 5. empty flag from last read to first write figure 8. minimum timing for a full flag coincident write pulse figure 7. minimum timing for an empty flag coincident read pulse figure 6. retransmit t rtc t rt t rts rt w , r hf , ef , ff t rtr flag valid 2679 drw 08 t rtf ef w r t wef t rpe 2679 drw 09 ff r w t rff t wpf 2679 drw 10
9 idt IDT7200L/7201la/7202la figure 9. half-full flag timing figure 10. expansion out figure 11. expansion in operating modes: care must be taken to assure that the appropriate flag is monitored by each system (i.e. ff is monitored on the device where w is used; ef is monitored on the device where r is used). for additional information, refer to tech note 8: operating fifos on full and empty boundary conditions and tech note 6: designing with fifos. single device mode a single idt7200/7201a/7202a may be used when the application requirements are for 256/512/1,024 words or less. these devices are in a single device configuration when the expansion in ( xi ) control input is grounded (see figure 12). depth expansion the idt7200/7201a/7202a can easily be adapted to applications when the requirements are for greater than 256/512/1,024 words. figure 14 demonstrates depth expansion using three idt7200/7201a/7202as. any depth can be attained by adding additional idt7200/7201a/7202as. these fifos operate in the depth expansion mode when the following conditions are met: 1. the first device must be designated by grounding the first load ( fl ) control input. 2. all other devices must have fl in the high state. 3. the expansion out ( xo ) pin of each device must be tied to the expansion in ( xi ) pin of the next device. see figure 14. 4. external logic is needed to generate a composite full flag ( ff ) and empty flag ( ef ). this requires the oring of all ef s and oring of all ff s (i.e. all must be set to generate the correct composite ff or ef ). see figure 14. 5. the retransmit ( rt ) function and half-full flag ( hf ) are not available in the depth expansion mode. for additional information, refer to tech note 9: cascading fifos or fifo modules. r w hf t rhf half-full or less more than half-full t whf 2679 drw 11 half-full or less r w xo 2679 drw 12 write to last physical location t xol t xoh read from last physical location t xol t xoh w r xi write to first physical location t xis read from first physical location t xis t xi t xir 2679 drw 13
10 idt IDT7200L/7201la/7202la usage modes: width expansion word width may be increased simply by connecting the corresponding input control signals of multiple devices. status flags ( ef , ff and hf ) can be detected from any one device. figure 13 demonstrates an 18-bit word width by using two idt7200/7201a/7202as. any word width can be attained by adding additional idt7200/7201a/7202as (figure 13). bidirectional operation applications which require data buffering between two systems (each system capable of read and write operations) can be achieved by pairing idt7200/7201a/7202as as shown in figure 16. both depth expansion and width expansion may be used in this mode. data flow-through two types of flow-through modes are permitted, a read flow-through and write flow-through mode. for the read flow-through mode (figure 17), the fifo permits a reading of a single word after writing one word of data into an empty fifo. the data is enabled on the bus in (t wef + t a ) ns after the rising edge of w , called the first write edge, and it remains on the bus until the r line is raised from low-to-high, after which the bus would go into a three-state mode after t rhz ns. the ef line would have a pulse showing temporary deassertion and then would be asserted. in the write flow-through mode (figure 18), the fifo permits the writing of a single word of data immediately after reading one word of data from a full fifo. the r line causes the ff to be deasserted but the w line being low causes it to be asserted again in anticipation of a new data word. on the rising edge of w , the new word is loaded in the fifo. the w line must be toggled when ff is not asserted to write new data in the fifo and to increment the write pointer. compound expansion the two expansion techniques described above can be applied together in a straightforward manner to achieve large fifo arrays (see figure 15). figure 13. block diagram of 256 x 18, 512 x 18, 1,024 x 18 fifo memory used in width expansion mode figure 12. block diagram of single 256 x 9, 512 x 9, 1,024 x 9 fifo write ( w ) data in (d) full flag ( ff ) reset ( rs ) 9 read ( r ) 9 data out (q) empty flag ( ef ) retransmit ( rt ) expansion in ( xi ) ( hf ) idt 7200/ 7201a/ 7202a (half-full flag) 2679 drw 14 idt 7200/ 7201a/ 7202a xi xi 99 18 9 18 hf hf 9 data write ( w ) full flag ( ff ) reset ( rs ) (d) in read ( r ) empty flag ( ef ) retransmit ( rt ) data out (q) idt 7200/ 7201a/ 7202a 2679 drw 15
11 idt IDT7200L/7201la/7202la table i?reset and retransmit single device configuration/width expansion mode inputs internal status outputs mode rs rs rs rs rs rt rt rt rt rt xi xi xi xi xi read pointer write pointer ef ef ef ef ef ff ff ff ff ff hf hf hf hf hf reset 0 x 0 location zero location zero 0 1 1 retransmit 1 0 0 location zero unchanged x x x read/write 1 1 0 increment (1) increment (1) xxx note: 2679 tbl 09 1. pointer will increment if flag is high. figure 14. block diagram of 768 x 9, 1,536 x 9, 3,072 x 9 fifo memory (depth expansion) table ii?reset and first load truth table depth expansion/compound expansion mode inputs internal status outputs mode rs rs rs rs rs fl fl fl fl fl xi xi xi xi xi read pointer write pointer ef ef ef ef ef ff ff ff ff ff reset first device 0 0 (1) location zero location zero 0 1 reset all other devices 0 1 (1) location zero location zero 0 1 read/write 1 x (1) x x x x note: 2679 tbl 10 1. xi is connected to xo of previous device. see figure 14. rs = reset input, fl / rt = first load/retransmit, ef = empty flag output, ff = full flag output, xi = expansion input, hf = half-full flag output 2679 drw 16 d w idt 7200/ 7201a/ 7202a ff ef fl xo rs full empty v cc r 9 9 99 xi 9 q idt 7200/ 7201a/ 7202a idt 7200/ 7201a/ 7202a ff ef fl xo xi ff ef fl xo xi
12 idt IDT7200L/7201la/7202la figure 15. compound fifo expansion notes: 1. for depth expansion block see section on depth expansion and figure 14. 2. for flag detection see section on width expansion and figure 13. figure 17. read data flow-through mode figure 16. bidirectional fifo mode idt7200/ idt7201a/ idt7202a depth expansion block r , w , rs d 0- d n q 0- q 8 idt7200/ idt7201a/ idt7202a depth expansion block idt7200/ idt7201a/ idt7202a depth expansion block 2679 drw 17 d 0- d 8 d 9- d n d 18- d n d( n-8)- d n d 9- d 17 d (n-8)- d n q 0- q 8 q 9- q 17 q 9- q 17 q (n-8) -q n q (n-8) -q n idt 7201a r b ef b hf b w a ff a w b ff b system a system b q b 0-8 d b 0-8 q a 0-8 r a hf a ef a idt 7200/ 7201a/ 7202a d a 0-8 idt 7200/ 7201a/ 7202a 2679 drw 18 w data r t rpe in ef data out t wlz t wef t a t ref data valid out 2679 drw 19
13 2975 stender way 800-345-7015 santa clara, ca 95054 fax: 408-492-8674 www.idt.com the idt logo is a registered trademark of integrated device technology, inc. figure 18. write data flow-through mode ordering information r data w in ff data out t ds t dh t a t wff t rff t wpf data in valid data out valid 2679 drw 20 idt xxxx device type xxx speed x power x package x process/ temperature range blank i b 7200 7201 7202 7280 7281 7282 12 15 20 25 30 35 40 50 65 80 120 commercial (0 o c to +70 o c) industrial (-40 o c to +85 o c) military (-55 o c to +125 o c) compliant to mil-std-883, class b 256 x 9-bit fifo 512 x 9-bit fifo 1,024 x 9-bit fifo 256 x 9-bit dual fifo 512 x 9-bit dual fifo 1,024 x 9-bit dual fifo commercial only commercial only commercial and military commercial and industrial military only commercial only military only commercial and military la low power p tp d td j so l xe plastic dip plastic thin dip cerdip thin cerdip plastic leaded chip carrier soic leadless chip carrier cerpack access time (t a ) speed in nanoseconds 2679 drw 21 military only-- except xe package blank i b (1) p28-1 p28-2 d28-1 d28-3 j32-1 so28-3 l32-1 e28-2 plcc lcc (7201 & 7202 only) (7201 & 7202 only) (7201 & 7202 only) (7201 & 7202 only) (2) see 7280/7281/7282 data sheet for details (3208.pdf) notes: 1. industrial temperature range is available for plastic packages by special order for speed grades faster than 25ns. 2. "a" to be included for 7201 and 7202 ordering part number.

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